New Statistical Timing Analysis Method Considering Process Variations and Crosstalk

I. ABSTRACT (SESSION 2) A. Statistical Gate Delay Static Timing Analysis (STA) tools are widely used for efficient timing checks on large chips. In early times, the nonlinear delay model (NLDM) was widely used for STA. As technology downscaled into ultra-deep sub-micron region, noise and coupling considerations require advanced gate mod-eling for STA. Croix and Wong proposed a current source drive models (CSDM) which model every gate by a voltage-dependent current source and capacitor [1]. However, some effects, such as internal charge sharing and multiple input simultaneous switching (MISS) can not be captured by such a simple model. These issues are addressed by transistor-level gate models which achieve higher accuracy [2], [3]. If the process variations are not considered, those gate models achieve high accuracy for STA. However, the down-scaling of technology brings a significant increase in the device and interconnect manufacturing process variations, such as length (L ef f), threshold voltage (V th), wire width (W w) and wire thickness (T w). Therefore, there is a need for advanced analysis tools which can handle variability caused by imperfect manufacturing processes. In order to capture the impact of process variations on gate behavior, statistical STA (SSTA) becomes more and more attractive. Most published SSTA methods can be called function-based SSTA since the gate delay is modeled as a linear or non-linear function of process variations and the coefficients are characterized and stored in look-up tables with entries of S in and C ef f. This modeling approach is similar to the NLDM concept thus has the accuracy limitations same as NLDM. Not considering the statistical S in and C ef f can result in 30% delay errors and even worse for bigger circuits [4]. The function-based delay representation is entirely based on non-physical or empirical models, which is the major source of inaccuracy [5]. In order to increase accuracy, CSDMs have be extended for SSTA in [4]–[6]. However, these methods are just verified in several simple single gates, and the correlations among input signals and between input signal and delay are not considered. To gain even higher accuracy than the above CSDM methods , and to be able to see the important effects such as MISS, we propose a statistical timing analysis solution based on transistor level gate models [3] to provide the variational voltage waveforms [7]. The gate models are constructed from CSDM-like transistor models. Due to the process …